As is well known, solid state storage devices such as SD cards or solid state drives (SSD) are widely used in a variety of electronic devices. Generally, a solid state storage device comprises a controlling circuit and a non-volatile memory.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 is connected with a host 14 through an external bus 12. Generally, the external bus 12 is a USB bus, a SATA bus, a PCIe bus, or the like. Moreover, the solid state storage device 10 comprises a controlling circuit 101 and a non-volatile memory 105. The controlling circuit 101 is connected with the non-volatile memory 105 through an internal bus 107. According to a command from the host 14, the controlling circuit 101 stores the received write data into the non-volatile memory 105, or the controlling circuit 101 acquires a read data from the non-volatile memory 105 and transmits the read data to the host 14.
Generally, the controlling circuit 101 stores a default read voltage set. During a read cycle, the controlling circuit 101 judges the read data of the non-volatile memory 105 according to the default read voltage set.
The controlling circuit 101 further comprises an error correction (ECC) circuit 104 and a retry table 106. The ECC unit 104 is used for correcting the error bits of the read data. After the error bits of the read data are corrected, accurate read data are transmitted to the host 14. However, if the ECC unit 104 is unable to successfully correct all bits of the read data, the ECC unit 10 cannot output the accurate read data to the host 14. Under this circumstance, the retry table 106 provides another retry read voltage set to the controlling circuit 101. According to the retry read voltage set, the controlling circuit 101 performs a read retry operation on the non-volatile memory 105.
The non-volatile memory 105 such as a flash memory comprises a memory array (not shown). The memory array comprises plural memory cells. In the memory array, each memory cell comprises a floating gate transistor. Depending on the amount of data to be stored in the memory cell, the flash memories may be classified into three types, i.e. a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory and a triple-level cell (TLC) flash memory. The SLC flash memory can store only one bit of data per cell. The MLC flash memory can store two bits of data per cell. The TLC flash memory can store three bits of data per cell.
Moreover, the floating gate of the floating gate transistor of each memory cell can store hot carriers. A threshold voltage (VTH) of the floating gate transistor is determined according to the amount of the stored hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the non-volatile memory 105, the amount of hot carriers to be injected into the floating gate is controlled by the controlling circuit 101. Consequently, the threshold voltage of the floating gate transistor is correspondingly changed. During a read cycle, the controlling circuit 101 provides a read voltage to the floating gate of the floating gate transistor and determines the storing state of the floating gate transistor by judging whether the floating gate transistor is turned on.
FIG. 2A schematically illustrates the threshold voltage distribution curves of the MLC flash memory in different storing states. Each cell of the MLC flash memory has four storing states E, A, B and C according to the amount of the injected hot carriers. Before the hot carriers are injected into the cell, the cell is in a storing state E. According to the number of hot carriers injected into the cell, the cell has the storing state A, the storing state B or the storing state C. The cell in the storing state C has the highest threshold voltage. The cell in the storing state E has the lowest threshold voltage. After an erase cycle, the cell is returned to the storing state E where no hot carriers are injected into the cell.
Moreover, each cell of the SLC flash memory has two storing states, and each cell of the TLC flash memory has eight storing states. Hereinafter, only the data reading process of the MLC flash memory (i.e., the non-volatile memory 105) will be described. It is noted that the concepts of the data reading process are also applied to the SLC flash memory and the TLC flash memory.
In practical, even if many cells are in the same storing state during the program cycle, the threshold voltages of these cells are not all identical. That is, the threshold voltages of these cells are distributed in a specified distribution curve with a median threshold voltage. As shown in FIG. 2A, the cells in the storing state E have a median threshold voltage VTHE (e.g. 0V), the cells in the storing state A have a median threshold voltage VTHA (e.g. 10V), the cells in the storing state B have a median threshold voltage VTHB (e.g. 20V), and the cells in the storing state C have a median threshold voltage VTHC (e.g. 30V). In other words, a greater number of the cells in the storing state A have the median threshold voltage VTHA (e.g. 10V).
Please refer to FIG. 2A again. According to the above characteristics of the MLC flash memory, a read voltage set including three read voltages Vra, Vrb and Vrc is defined. During the read cycle, the controlling circuit 101 provides the three read voltages of the read voltage set to the MLC flash memory in order to detect the storing states of the cells of the MLC flash memory.
For example, when the read voltage Vrb is provided to the non-volatile memory 105, a most significant bit (MSB) of the cell can be determined. If the threshold voltage of the cell is lower than the read voltage Vrb and the cell can be turned on, the controlling circuit 101 judges that the MSB of the cell is “1”. Whereas, if the threshold voltage of the cell is higher than the read voltage Vrb and the cell cannot be turned on, the controlling circuit 101 judges that the MSB of the cell is “0”. Similarly, after the read voltage Vra and the read voltage Vrc are provided to the non-volatile memory 105, a least significant bit (LSB) of the cell can be determined. Consequently, the storing state E is denoted as a logic state is “11”, the storing state A is denoted as a logic state “10”, the storing state B is denoted as the logic state “00”, and the storing state C is denoted as the logic state “01”.
Similarly, the controlling circuit 101 can employ one read voltage to determine two storing states of the SLC flash memory. The controlling circuit 101 can use a read voltage set including seven read voltages to determine eight storing states of the TLC flash memory.
As mentioned above, the read voltages Vra, Vrb and Vrc are important for determining the storing states of the cells. However, after the non-volatile memory 105 has been used for a certain time period, the characteristics of the cells are subjected to changes. Under this circumstance, the threshold voltage distribution curves of the storing state of all cells in the non-volatile memory 105 are possibly changed, and the median threshold voltages are shifted. If the original read voltages Vra, Vrb and Vrc are still used to read the data of the non-volatile memory 105, the number of error bits increases. Since the number of the erroneously-judged cells is large, the ECC circuit 104 cannot effectively correct the erroneously-judged cells. Under this circumstance, the controlling circuit 101 cannot output the accurate read data to the host 14.
For solving the above drawbacks, the controlling circuit 101 has a retry table for storing plural read voltage sets. If the controlling circuit 101 confirms that a read retry operation is required, the controlling circuit 101 acquires another read voltage set including three read voltages Vra′, Vrb′ and Vrc′ from the retry table 106. Moreover, the read voltages Vra′, Vrb′ and Vrc′ are provided to the non-volatile memory 105 in order to read the data again.
FIG. 2B is a flowchart illustrating an error correction method for a solid state storage device according to the prior art. During the read cycle, the controlling circuit 101 performs a decoding process A. In the decoding process A, a hard decoding operation is performed according to the default read voltage set. That is, the controlling circuit 101 provides the default read voltage set to a block of the non-volatile memory 105 to acquire the read data of the block, and the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits in the read data can be corrected, it means that the decoding operation is successfully done and the decoding process A passes. Consequently, the read data is accurately transmitted from the controlling circuit 101 to the host 14. Whereas, if the error bits in the read data cannot be corrected, no accurate read data is acquired and the decoding process A fails. Then, the controlling circuit 101 performs a read retry process.
In the read retry process, a decoding process B is firstly performed. In the decoding process B, a hard decoding operation is performed according to the retry read voltage set.
For example, M retry read voltage sets have been previously stored in the retry table 106. In the decoding process B, the controlling circuit 101 acquires a first retry read voltage set including three read voltages Vra′, Vrb′ and Vrc′ from the retry table 106, and the ECC circuit 104 performs the hard decoding operation to correct the read data. If the error bits in the read data can be corrected, it means that the decoding operation is successfully done and the decoding process B passes. Consequently, the accurate read data is transmitted from the controlling circuit 101 to the host 14. Whereas, if the error bits in the read data cannot be corrected, no accurate read data is acquired and the decoding process B fails. Then, the controlling circuit 101 performs a read retry process. Whereas, if the error bits in the read data cannot be corrected, the controlling circuit 101 acquires a second retry read voltage set including three read voltages Vra″, Vrb″ and Vrc″ from the retry table 106 and judges whether the decoding operation is successfully done.
As mentioned above, M retry read voltage sets are stored in the retry table 106. If the decoding operation is successfully done according to one of the M retry read voltage sets, it means that the decoding process B passes. Whereas, if the data cannot be successfully decoded according to the entire of the M retry read voltage sets, it means that the decoding process B fails. Then, the controlling circuit 101 performs a decoding process C. Obviously, the time period of performing the decoding process B is longer than the time period of performing the decoding process A.
In the decoding process C, a soft decoding operation is performed according to the retry read voltage set. Generally, the soft decoding operation has better error correction capability than the hard decoding operation. However, while the soft decoding operation is performed, the controlling circuit 101 acquires a read data according to many retry read voltage sets. In other words, the time period of performing the soft decoding operation is longer. That is, the time period of performing the decoding process C is longer than the time period of performing the decoding process B.
For example, additional N retry read voltage sets are stored in the retry table 106. If the decoding operation is successfully done according to one of the N retry read voltage sets, it means that the decoding process C passes. Whereas, if the data cannot be successfully decoded according to the entire of the N retry read voltage sets, it means that the decoding process C fails. Under this circumstance, the controlling circuit 101 confirms that the read data cannot be accurately acquired and generates a failed message to the host 14 to indicate that the decoding process fails.
As mentioned above, if the decoding process A fails, the controlling circuit 101 performs the read retry process. In the read retry process, the controlling circuit 101 has to perform the decoding process B at first. If the controlling circuit 101 confirms that the decoding process B fails, the controlling circuit 101 performs the decoding process C. If the controlling circuit 101 confirms that the decoding process C fails, the controlling circuit 101 issues the failed message to the host 14.
Moreover, the M read voltage sets in the retry table 106 are provided by the manufacturer of the non-volatile memory 105. During the read retry decoding process B of the solid state storage device 10, the controlling circuit 101 sequentially reads the M retry read voltage sets from the retry table 106 and sequentially provides the M read voltage sets to the non-volatile memory 105. Obviously, during the decoding process B, the controlling circuit 101 is only able to sequentially provide the retry read voltage sets to the non-volatile memory 105, but is unable to directly acquire the suitable retry read voltage sets. In other words, the controlling circuit 101 spends a long time providing unsuitable retry read voltage sets to the non-volatile memory 105.
Similarly, during the read retry decoding process C of the solid state storage device 10, the above problems also occur. Since the time period of performing the error correction method is very long, the read speed of the solid state storage device 10 is largely decreased.